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BR25L010-W, BR25L020-W, BR25L040-W, BR25L080-W, BR25L160-W, BR25L320-W, BR25L640-W
4. Status register write / read command
CS
Technical Note
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SI
0
0
0
0
*
0
0
1
*
*
*
*
BP1 BP0
*
*
SO
High-Z
* =Don't care
Fig.41 Status register write command (BR25L010/020/040-W)
CS
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SI
0
0
0
0
0
0
0
1
WPEN
*
*
*
BP1 BP0
*
*
SO
High-Z
* =Don't care
Fig.42 Status register write command (BR25L080/160/320/640-W)
Write status register command can write status register data. The data the can be written by this command are 2 bits *1,
that is, BP1 (bit3) and BP0 (bit2) among 8 bits of status register. By BP1 and BP0, write disable block of EEPROM can be
set. As for this command, set CS LOW, and input ope code of write status register, and input data. Then, by making CS
HIGH, EEPROM starts writing. Write time requires time of tE/W as same as write. As for CS rise, start CS after taking the
last data bit (bit0), and before the next SCK clock starts. At other timing, command is cancelled. Write disable block is
determined by BP1 and BP0, and the block can be selected from 1/4 of memory array, 1/2, and entire memory array.
(Refer to the write disable block setting table.) To the write disabled block, write cannot be made, and only read can be
made.
* 3 bits including BR25L080, 160, 320, 640-W WPEN (bit7)
CS
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SI
SO
0
High-Z
0
0
0
*
1
0
1
bit7
1
bit6
1
bit5
1
bit4
1
bit3
bit2
bit1
bit0
BP1 BP0 WEN R/B
* =Don't care
Fig.43 Status register read command (BR25L010/020/040-W)
CS
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SI
SO
0
High-Z
0
0
0
0
1
0
1
bit7
WPEN
bit6
0
bit5
0
bit4
0
bit3
bit2
bit1
BP1 BP0 WEN
bit0
R/B
Fig.44 Status register read command (BR25L080/160/320/640-W)
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? 2010 ROHM Co., Ltd. All rights reserved.
9/16
2010.07 - Rev. B
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